Sr. Physical Design Engineer - Static Timing Analysis, Cloud Scale Machine Learning

Annapurna Labs (U.S.) Inc. offers an onsite Senior Physical Design role in Cupertino, CA with a startup‑like team culture that values collaboration across RTL, architecture, and physical design. The position provides a competitive salary range of USD 183,000 to 247,600 per year and a comprehensive benefits package that includes health insurance, 401(k) matching, paid time off, parental leave, sign‑on payments, and restricted stock units (RSUs).

Responsibilities

• Develop and maintain flows for block and full‑chip level static timing analysis.
• Write, debug, and validate timing constraints for blocks and the full chip.
• Execute Static Timing Analysis and provide regular feedback to team members and leads.
• Offer guidance on addressing timing issues, including generating ECOs and correcting constraint issues.
• Develop scripts to automate timing analysis and generate reports.
• Contribute as a valued member of a startup‑like team through strong collaboration with other physical design engineers and with the RTL and Architecture teams.

Requirements

• Experience with scripting languages such as Perl, Python, or JavaScript.
• BS with 8+ years, MS with 6+ years, or PhD with 4+ years in EE/CS.
• Expertise in timing analysis fundamentals.
• 3+ years of experience performing Static Timing Analysis.
• 3+ years developing timing constraints.
• Experience with timing analysis using EDA tools such as PrimeTime, Tempus, or equivalent.
• Understanding of ASIC physical design from RTL to GDSII.
• Understanding of other sign‑off activities, including IR/EM, physical verification, and DFT.

Technologies

• Perl
• Python
• Javascript
• PrimeTime
• Tempus
• PT‑DMSA
• Tempus‑ECO
• Tweaker
• STAR‑RC
• Quantus
• SPICE
• SPECTRE
• DDR
• HBM
• PCIe
• Die‑to‑Die

Benefits

• Health insurance
• 401(k) matching
• Paid time off
• Parental leave
• Sign‑on payments
• Restricted stock units (RSUs)